The present invention relates to a semiconductor memory including a ferroelectric capacitor and a method for driving the semiconductor memory.
A known semiconductor memory including a ferroelectric capacitor is composed of, as shown in FIG. 6, a field effect transistor (hereinafter referred to as the FET) 1 having a drain region 1a, a source region 1b and a gate electrode 1c, and a ferroelectric capacitor 2 having an upper electrode 2a, a lower electrode 2b and a ferroelectric film 2c. This semiconductor memory employs the non-destructive read-out system in which the lower electrode 2b of the ferroelectric capacitor 2 is connected to the gate electrode 1c of the FET 1, so as to use the ferroelectric capacitor 2 for controlling the gate potential of the FET 1. In FIG. 6, a reference numeral 3 denotes a substrate.
In writing a data in this semiconductor memory, a writing voltage is applied between the upper electrode 2a of the ferroelectric capacitor 2, which works as a control electrode, and the substrate 3.
For example, when a data is written by applying a voltage (control voltage) positive with respect to the substrate 3 to the upper electrode 2a, downward polarization is caused in the ferroelectric film 2c of the ferroelectric capacitor 2. Thereafter, even when the upper electrode 2a is grounded, positive charge remains in the gate electrode 1c of the FET 1, and hence, the gate electrode 1c has a positive potential.
When the potential of the gate electrode 1c exceeds the threshold voltage of the FET 1, the FET 1 is in an on-state. Therefore, when a potential difference is caused between the drain region 1a and the source region 1b, a current flows between the drain region 1a and the source region 1b. Such a logical state of the ferroelectric memory for allowing a current to flow between the drain region 1a and the source region 1b is defined, for example, as “1”.
On the other hand, when a voltage negative with respect to the substrate 3 is applied to the upper electrode 2a of the ferroelectric capacitor 2, upward polarization is caused in the ferroelectric film 2c of the ferroelectric capacitor 2. Thereafter, even when the upper electrode 2a is grounded, negative charge remains in the gate electrode 1c of the FET 1, and hence, the gate electrode 1c has a negative potential. In this case, the potential of the gate electrode 1c is always lower than the threshold voltage of the FET 1, the FET 1 is in an off-state. Therefore, even when a potential difference is caused between the drain region 1a and the source region 1b, no current flows between the drain region 1a and the source region 1b. Such a logical state of the ferroelectric memory for allowing no current to flow between the drain region 1a and the source region 1b is defined, for example, as “0”.
Even when the power supply to the ferroelectric capacitor 2 is shut off, namely, even when the voltage application to the upper electrode 2a of the ferroelectric capacitor 2 is stopped, the aforementioned logical states are retained, and thus, a nonvolatile memory is realized. Specifically, when power is supplied again to apply a voltage between the drain region 1a and the source region 1c after shutting off the power supply for a given period of time, a current flows between the drain region 1a and the source region 1b if the logical state is “1”, so that the data “1” can be read, and no current flows between the drain region 1a and the source region 1b if the logical state is “0”, so that the data “0” can be read.
In order to correctly retain a data while the power is being shut off (which characteristic for retaining a data is designated as retention), it is necessary to always keep the potential of the gate electrode 1c of the FET 1 to be higher than the threshold voltage of the FET 1 when the data is “1” and to always keep the potential of the gate electrode 1c of the FET 1 at a negative voltage when the data is “0”.
While the power is being shut off, the upper electrode 2a of the ferroelectric capacitor 2 and the substrate 3 have a ground potential, and hence, the potential of the gate electrode 1c is isolated. Therefore, ideally, as shown in FIG. 7, a first intersection c between a hysteresis loop 4 obtained in writing a data in the ferroelectric capacitor 2 and a gate capacitance load line 5 of the FET 1 obtained when a bias voltage is 0 V corresponds to the potential of the gate electrode 1c obtained in storing a data “1”, and a second intersection d between the hysteresis loop 4 and the gate capacitance load line 5 corresponds to the potential of the gate electrode 1c obtained in storing a data “0”. In FIG. 7, the ordinate indicates charge Q appearing in the upper electrode 2a (or the gate electrode 1c) and the abscissa indicates voltage V.
Actually, however, the ferroelectric capacitor 2 is not an ideal insulator but has a resistance component, and hence, the potential of the gate electrode 1c drops through the resistance component. This potential drop is exponential and has a time constant obtained by multiplying parallel combined capacitance of the gate capacitance of the FET 1 and the capacitance of the ferroelectric capacitor 2 by the resistance component of the ferroelectric capacitor 2. The time constant is approximately 104 seconds at most. Accordingly, the potential of the gate electrode 1c is halved within several hours.
Since the potential of the gate electrode 1c is approximately 1 V at the first intersection c as shown in FIG. 7, when the potential is halved, the potential of the gate electrode 1c becomes approximately 0.5 V, which is lower than the threshold voltage of the FET 1 (generally of approximately 0.7 V). As a result, the FET 1 that should be in an on-state is turned off in a short period of time.
In this manner, although the ferroelectric memory using the ferroelectric capacitor 2 for controlling the gate potential of the FET 1 has an advantage that a rewrite operation is not necessary after a data read operation, it has the following problem: The gate electrode 1c of the FET 1 obtains a potential after writing a data, and the ability for keeping the gate potential determines the retention characteristic. Since the time constant until discharge of the ferroelectric capacitor 2 is short due to the resistance component of the ferroelectric capacitor 2, the data retaining ability is short, namely, the retention characteristic is not good.
Furthermore, in accordance with increased integration and refinement of semiconductor integrated circuit devices, the area of a semiconductor memory built on a semiconductor integrated circuit device is desired to be reduced. In the conventional semiconductor memory, however, each memory cell includes the ferroelectric capacitor 2 and the FET 1 for reading a data stored in the ferroelectric capacitor 2, and hence, the area of each memory cell, namely, the area of the entire semiconductor memory, cannot be sufficiently reduced.